IEEE 1804-2017 PDF

IEEE 1804-2017 PDF

This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated using an ATPG tool, or have been supplied externally and have been simulated using an ATPG tool to ascertain the fault coverage.
Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesized, or in netlist forms. Commercial tools today for Automatic Test Pattern Generation (ATPG) using algorithmic techniques operate on a structural netlist of the Design Under Test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to 19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes shall enable test qualification based on ATPG tool generated 24 patterns and based upon fault coverage metrics in a uniform way and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality. Such metric are commonly used in today’s system-on-chips (SOCs) with a heterogeneous mix of modules thereein, often consisting of intellectual property (IP) cores (which are often sourced from design teams different from those designing the chips themselves), and test patterns for which are generated using different ATPG tools. This points to the need for such a standard. This standard shall help to build consensus amongst the chip designers, tool vendors and end customers of integrated circuits. The coverage metrics reported by the designers shall be consistent across all tools. Coverage requirements set by the customers can now also be uniformly targeted by the designers, independent of the ATPG tool used. The standard will also help in merging coverage reports from different tools when different IPs are integrated into an SOC. In the first version of this standard, only the classical stuck-at 0 and stuck-at 1 fault model shall be considered. The following are outside the scope of this document: a) Standards on ATPG algorithms, ATPG efficiency 1 (speed, memory), fault grading efficiency, fault models other than the stuck-at fault model, test vector compaction. b) Standards on how a gate-level netlist is created for a design.
New IEEE Standard – Active. The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.